Design of Double 16_32 –Bit RISC Processor

Abstract

The SOCs built today offer a high level of functionality, serve a variety of applications, and improve in efficiency and cost. Embedded systems also face area and power consumption constraints in addition to real-time challenges. The main objective is to design and implement a 32-bit High-performance RISC (Reduced Instruction Set Computer) Processor architecture. The Processor is designed as an instantiation of submodules using Verilog HDL (Hardware Description Language). a 16-bit compatibility is introduced which makes use of the ISA to execute two 16bit operations at the same time and thus provides the capability to switch and execute both 32-bit and two 16-bit operations using the execution unit. The ISA is modified to meet the requirement to execute both 16-bit operation and 32-bit operations. Each of these instructions are independent of the other instruction and can be executed simultaneously. This enables the RISC based architecture to also enhance the speed of the design by a factor of 2 for 16 bit operations.

Introduction

I. INTRODUCTION

Processors are an essential part of any electronic gadgets used to control and operate various functionality according to the user’s needs MIPS is an architecture that is used to design a MIPS-based RISC processor. MIPS design is based on the RISC principle, so it has fixed length instructions with a few different formats. It also emphasizes the load/store architecture. The access time of the register is much faster than the access time of memory, so it is more advantageous in terms of speed to perform any operations in an on-chip register rather than in memory. To eliminate the impact of memory operation, MIPS uses load store architecture where memory access is only required when load and store instructions are being fetched. However, nowadays, performance is an essential parameter for any electronic gadget, so to improve the overall performance. Still, hazards have to be dealt with using a pipeline MIPS processor. Data hazard occurs in a pipeline when an instruction depends on the result of the previous instruction that is already in process and not fully executed. Hazards can be rectified by adding an extra hardware unit known as a forwarding unit that directly forwards the result of ALU through some multiplexer as an input of ALU for the next instruction if required. Computer architecture composes of computer organization and the Instruction Set Architecture, ISA. ISA gives a logical view of what a computer is capable of doing and when you look at computer organization, it basically talks about how ISA is implemented. Both these put together is normally called computer. There are two main architectures around which most of the Processors are designed around: Complex Instruction Set Computer (CISC) and Reduced Instruction Set Computer (RISC). RISC is one of the types of microprocessors that uses an extremely improved set of instructions. It is used as an alternative of CISC and it’s considered to be the most efficient CPU architecture

II. METHODOLOGY

The flow diagram as shown in figure 1 indicate the RTL to GDS flow where the RTL code is functionally verified using the NC launch simulator and the synthesis process starts to create the gate-level netlist for the design is obtained where the required constraints and the required technology library files are necessary for the optimization and mapping to the particular technology library to take place. The gate-level netlist becomes the input file for the Cadence INNOVUS tool to start with the physical design process. Below steps indicate the flow

1. In this design, four stages of pipeline which are Instruction Fetch(IF), Instruction Decode(ID), Execute Stage(EX), Memory Access,   and Write Back Stage(MEM WB) have been carried out. The sub-module of the processor will be first designed, coded, and tested by employing bottom-up design methodology.
2. Once all sub-modules were designed and established to be fully functional, they were instantiated into a top module to develop the RISC processor.
3. The processor will then be tested by executing a comprehensive set of instructions while verifying proper functionality and timing.
4. The synthesis of the top-level module gives the gate level netlist for the PD process.
5. The physical design process starts once the design is functionally verified.
6. Physical design part includes partitioning, floor planning and routing.
7. In partitioning complex circuit will be reduced into simple blocks.
8. During the floor planning process, all the blocks will be assigned with proper boundary.
9. In the routing part, depending upon the requirement local and global routings will be carried.
10. The physical design process takes the netlist, .sdc, .lib, .lef files for both placement and routing of the design.
11. The placement of the design takes place based on the technology library file and library exchange format file which contains all the metal layer information, design rules, and abstract-level information.
12. Based on this file, placement of the standard cells in the gate-level netlist will be placed on the core area of the design    partition.

The architecture of the design is illustrated below figure 2

Conclusion

The 4- stage pipelined RISC architecture processor increases the speed of the operation as compared to the Von-Neumann architecture by using the separate data and address buses for both instruction and data using instruction memory and data memory respectively. The capability has been provided to execute two 16-bit operations at the same time which increases the efficiency and thus executes both 32-bit and two 16-bit operations using the same execution unit and as a result of which leads to increase in speed by a factor of 2. The total power consumed by the system is reported to be with frequency of 100MHz was 1.1649W.Tools Vivado ,Innovus and genus have been utilized to implement the design.

References

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Copyright

Copyright © 2023 Nagendra Prasad N, Dr. Sujatha Hiremath, Arjumath Farraj. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.